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SI5020
SiPHYTM MULTI-RATE SONET/SDH CLOCK
Features
Complete high speed, low power, CDR solution includes the following:
! ! ! ! !
AND
DATA RECOVERY IC
Supports OC-48/12/3, STM-16/4/1, Gigabit Ethernet, and 2.7 Gbps FEC Low Power--270 mW (TYP OC-48) Small Footprint: 4 mm x 4 mm DSPLLTM Eliminates External Loop Filter Components 3.3 V Tolerant Control Inputs
! ! ! ! !
Exceeds All SONET/SDH Jitter Specifications Jitter Generation 3.0 mUIRMS (TYP) Device Power Down Loss-of-Lock Indicator Single 2.5 V Supply Ordering Information: See page 14.
Applications
! ! ! !
RATESEL1
RATESEL0
CLKOUT+
Description
REXT
20 19 18 1 2 3 4 5 6
LOL
GND
!
17 16 15 PWRDN/CAL 14 VDD
The SI5020 is a fully integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-48/12/3, STM-16/4/1, or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also provided for OC-48/STM-16 applications that employ forward error correction (FEC). DSPLLTM technology eliminates sensitive noise entry points thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The SI5020 represents a new standard in low jitter, low power, and small size for high speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (-40C to 85C).
VDD GND REFCLK+ REFCLK-
GND Pad
CLKOUT-
SONET/SDH/ATM Routers Add/Drop Multiplexers Digital Cross Connects Gigabit Ethernet Interfaces
! ! !
SONET/SDH Test Equipment Optical Transceiver Modules SONET/SDH Regenerators Board Level Serial Links
Pin Assignments SI5020
13 DOUT+ 12 DOUT- 11 VDD
7
VDD
8
GND
9
DIN+
10
DIN-
Top View
Functional Block Diagram
LOL
DIN+ DIN-
2
BUF
DSPLLTM Phase-Locked Loop
Retimer
BUF
2
DOUT+ DOUT- PWRDN/CAL
Bias
2
2
BUF
2
CLKOUT+ CLKOUT-
REXT
RATESEL1-0
REFCLK+ REFCLK-
Preliminary Rev. 0.8 12/00
Copyright (c) 2000 by Silicon Laboratories
SI5020-DS08
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
S i5 02 0
2
Preliminary Rev. 0.8
SI5020 TA B L E O F CON T E N T S
Section Page
4 5 9 9 9 9 9 9 10 10 11 11 11 11 11 13 15 16 18
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPLLTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forward Error Correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: SI5020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Rev. 0.8
3
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Detailed Block Diagram
R e tim e
DOUT+ DOUT-
c
D IN + D IN -
Phase D e te c to r
A /D
DSP n
VCO
CLK D ivid e r
CLKOUT+
c
CLKOUT-
REFCLK+ REFCLK- Lock D e te c to r 2 R A T E S E L 1-0 REXT
B ias G en e ra tio n C a lib ratio n
LOL
P W R D N /C A L
Figure 1. Detailed Block Diagram
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Preliminary Rev. 0.8
SI5020
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature SI5020 Supply Voltage2 Symbol TA VDD Test Condition Min1 -40 2.375 Typ 25 2.5 Max1 85 2.625 Unit C V
Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25C unless otherwise stated. 2. The SI5020 specifications are guaranteed when using the recommended application circuit (including component tolerance) of Figure 5 on page 9.
V SIGNAL+ VICM,VOCM Differential I/Os SIGNAL- VIS Single-Ended Voltage
(SIGNAL+) - (SIGNAL-)
Differential Voltage Swing
VID,VOD (VID = 2VIS)
Differential Peak-to-Peak Voltage t
Figure 2. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
tCf-D DOUT
tCr-D
CLKOUT
Figure 3. Clock to Data Timing
DOUT, CLKOUT
80% 20% tF tR Figure 4. DOUT and CLKOUT Rise/Fall Times
Preliminary Rev. 0.8
5
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Table 2. DC Characteristics
(VDD = 2.5 V 5%, TA = -40C to 85C)
Parameter Supply Current OC-48 and FEC (2.7 GHz) GigE OC-12 OC-3 Power Dissipation OC-48 and FEC (2.7 GHz) GigE OC-12 OC-3 Common Mode Input Voltage (DIN, REFCLK) Single Ended Input Voltage (DIN, REFCLK) Differential Input Voltage Swing (DIN, REFCLK) Input Impedance (DIN, REFCLK) Differential Output Voltage Swing (DOUT) Differential Output Voltage Swing (CLKOUT) Output Common Mode Voltage (DOUT,CLKOUT) Output Impedance (DOUT,CLKOUT) Output Short to GND (DOUT,CLKOUT) Output Short to VDD (DOUT,CLKOUT) Input Voltage Low (LVTTL Inputs) Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Output Voltage Low (LVTTL Outputs) Output Voltage High (LVTTL Outputs) Input Impedance (LVTTL Inputs) PWRDN/CAL Leakage Current
Symbol IDD
Test Condition
Min -- -- -- --
Typ 108 113 117 124 270 283 293 310 .80*VDD -- -- 100 940 900 VDD - 0.20 100 25 -15 -- -- -- -- -- -- -- 25
Max 118 123 127 134 310 323 333 352 -- 750 1500 116 TBD TBD -- 116 TBD -- .8 -- 10 10 0.4 -- -- TBD
Unit mA
PD -- -- -- -- -- 100 200 84 TBD TBD -- 84 -- TBD -- 2.0 -- -- -- 2.0 10 TBD mW
VICM VIS VID RIN VOD VOD VOCM ROUT ISC(-) ISC(+) VIL VIH IIL IIH VOL VOH RIN IPWRDN
varies with VDD See Figure 2 See Figure 2 Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line Single-ended
V mV mV (pk-pk) mV (pk-pk) mV (pk-pk) V mA mA V V A A V V k A
IO = 2 mA IO = 2 mA VPWRDN 0.8 V
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Preliminary Rev. 0.8
SI5020
Table 3. AC Characteristics (Clock & Data)
(VA 2.5 V 5%, TA = -40C to 85C)
Parameter Output Clock Rate Output Rise Time Output Fall Time Clock to Data Delay FEC (2.7 GHz) OC-48 GigE OC-12 OC-3 Clock to Data Delay FEC (2.7 GHz) OC-48 Input Return Loss
Symbol fCLK tR tF tCr-D
Test Condition
Min .15
Typ -- 100 100 250 255 500 890 4100 51 50 -- --
Max 2.7 TBD TBD TBD TBD TBD TBD TBD TBD TBD -- --
Unit GHz ps ps ps
Figure 4 Figure 4 Figure 3
-- -- TBD TBD TBD TBD TBD
tCf-D
Figure 3 TBD TBD 100 kHz - 2.5 GHz 2.5 GHz - 4.0 GHz 18.7 TBD ps dB dB
Preliminary Rev. 0.8
7
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Table 4. AC Characteristics (PLL Characteristics)
(VA 2.5 V 5%, TA = -40C to 85C)
Parameter Jitter Tolerance (OC-48)*
Symbol JTOL(P-P)
Test Condition f = 600 Hz f = 6000 Hz f = 100 kHz f = 1 MHz
Min 40 4 4 0.4 40 4 4 0.4 60 6 6 0.6 600
Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Max -- -- -- -- -- -- -- -- -- -- -- -- --
Unit UIp-p UIp-p UIp-p UIp-p UIp-p UIp-p UIp-p UIp-p UIp-p UIp-p UIp-p UIp-p ps
Jitter Tolerance (OC-12 Mode)
*
JTOL(P-P)
f = 30 Hz f = 300 Hz f = 25 kHz f = 250 kHz
Jitter Tolerance (OC-3 Mode)
*
JTOL(P-P)
f = 30 Hz f = 300 Hz f = 6.5 kHz f = 65 kHz
Jitter Tolerance (Gigabit Ethernet) Receive Data Total Jitter Tolerance Jitter Tolerance (Gigabit Ethernet) Receive Data Deterministic Jitter Tolerance RMS Jitter Generation* Peak-to-Peak Jitter Generation* Jitter Transfer Bandwidth*
TJT(P-P)
IEEE 802.3z Clause 38.68
DJT(P-P)
IEEE 802.3z Clause 38.69
370
TBD
--
ps
JGEN(rms) JGEN(rms) JBW
with no jitter on serial data with no jitter on serial data OC-48 Mode OC-12 Mode OC-3 Mode
-- -- -- -- -- -- 1.45 40 40 19.44 -100 TBD
3.0 25 -- -- -- 0.03 1.5 60 50 -- -- 600
5.0 55 2.0 500 130 0.1 1.7 150 60 168.75 100 TBD
mUI mUI MHz kHz kHz dB ms s % MHz ppm ppm
Jitter Transfer
Peaking*
JP TAQ After falling edge of PWRDN/CAL From the return of valid data
Acquisition Time
Input Reference Clock Duty Cycle Reference Clock Range Input Reference Clock Frequency Tolerance Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock)
CDUTY CTOL LOL
LOCK
TBD
300
TBD
ppm
*Note: Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 223 - 1 data pattern.
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Preliminary Rev. 0.8
SI5020
Table 5. Absolute Maximum Ratings
Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range Lead Temperature (soldering 10 seconds) ESD HBM Tolerance (100 pf, 1.5 k) TJCT TSTG Symbol VDD VDIG VDIF Value -0.5 to 2.8 -0.3 to 3.6 -0.3 to (VDD+ 0.3) 50 -55 to 150 -55 to 150 300 1 Unit V V V mA C C C kV
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter Thermal Resistance Junction to Ambient Symbol JA
LVTTL Control Inputs
Test Condition Still Air
Value 38
Unit C/W
Loss-of-Lock Indicator
2
RATESEL1-0
PWRDN/CAL
High Speed Serial Input
DIN+ DIN-
LOL
DOUT+ DOUT-
Recovered Data
SI5020
System Reference Clock REFCLK+ REFCLK- CLKOUT+ CLKOUT- Recovered Clock
REXT
10k (1%)
VDD
0.1 F 2200pF 20pF
Figure 5. SI5020 Typical Application Circuit
Preliminary Rev. 0.8
GND
VDD
9
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Functional Description
The SI5020 utilizes a phase-locked loop (PLL) to recover a clock synchronous to the input data stream. This clock is used to retime the data, and both the recovered clock and data are output synchronously via current mode logic (CML) drivers. Optimal jitter performance is obtained by using Silicon Laboratories' DSPLLTM technology to eliminate the noise entry points caused by external PLL loop filter components. RATESEL0-1 pins. The RATESEL0-1 configuration and associated data rates are given in Table 7.
Table 7. Multi-Rate Configuration
RATESEL [0:1]
00 10 01 11
SONET/ SDH
2.488 Gbps 1.244 Gbps 622.08 Mbps 155.52 Mbps
Gigabit Ethernet
-- 1.25 Gbps -- --
DSPLLTM
The phase-locked loop structure (shown in Figure 1 on page 4) utilizes Silicon Laboratories' DSPLLTM technology to eliminate the need for external loop filter components found in traditional PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage controlled oscillator (VCO). Because external loop filter components are not required, sensitive noise entry points are eliminated thus making the DSPLL less susceptible to board-level noise sources that make SONET/SDH jitter compliance difficult to attain.
OC-48 with 15/14 FEC
2.67 Gbps -- -- --
CLK Divider
1 2 4 16
Reference Clock Detect
The SI5020 uses the reference clock to center the VCO output frequency so that clock and data can be recovered from the input data stream. The device will self configure for operation with one of three reference clock frequencies. This eliminates the need to externally configure the device to operate with a particular reference clock. The reference clock centers the VCO for a nominal output of between 2.5 GHz and 2.7 Ghz. The VCO frequency is centered at 16, 32, or 128 times the reference clock frequency. Detection circuitry continuously monitors the reference clock input to determine whether the device should be configured for a reference clock that is 1/16, 1/32, or 1/128 the nominal VCO output. Approximate reference clock frequencies for some target applications are given in Table 8.
PLL Self-Calibration
The SI5020 achieves optimal jitter performance by using self-calibration circuitry to set the loop gain parameters within the DSPLL. For the self-calibration circuitry to operate correctly, the power supply voltage must exceed 2.25 V when calibration occurs. For best performance, the user should force a self-calibration once the supply has stabilized on power-up. A self-calibration can be initiated by forcing a high-tolow transition on the power-down control input, PWRDN/CAL, while a valid reference clock is supplied to the REFCLK input. The PWRDN/CAL input should be held high at least 1 S before transitioning low to guarantee a self-calibration. Several application circuits that could be used to initiate a power-on self-calibration are provided in Silicon Laboratories' "AN42: Controlling the Si5018/20 Self-Calibration."
Table 8. Typical REFCLK Frequencies
Gigabit Ethernet
19.53 MHz 78.125 MHz 156.25 MHz
SONET/SDH
19.44 MHz 77.76 MHz 155.52 MHz
SONET/ SDH with 15/14 FEC
20.83 MHz 83.31 MHz 166.63 MHz
Ratio of VCO to REFCLK
128 32 16
Multi-Rate Operation
The SI5020 supports clock and data recovery for OC-48 and STM-16 data streams. In addition, the PLL was designed to operate at data rates up to 2.7 Gbps to support OC-48/STM-16 applications that employ forward error correction (FEC). Multi-rate operation is achieved by configuring the device to divide down the output of the VCO to the desired data rate. The divide factor is configured by the
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Preliminary Rev. 0.8
SI5020
Forward Error Correction (FEC)
The SI5020 supports FEC in SONET OC-48 (SDH STM-16) applications for data rates up to 2.7 Gbps. In FEC applications, the appropriate reference clock frequency is determined by dividing the input data rate by 16, 32, or 128. For example, if an FEC code is used that produces a 2.70 Gbps data rate, the required reference clock would be 168.75 MHz, 84.375 MHz, or 21.09 MHz.
Sinusoidal Input Jitter (UI p-p)
Slope = 20 dB/Decade
15 1.5 0.15
Lock Detect
The SI5020 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. The circuit compares the frequency of a divided down version of the recovered clock with the frequency of the supplied reference clock (REFCLK). If the recovered clock frequency deviates from that of the reference clock by the amount specified in Table 4 on page 8, the PLL is declared out of lock, and the loss-oflock (LOL) pin is asserted "high." In this state, the DSPLL will periodically try to reacquire lock with the incoming data stream. During reacquisition, the recovered clock, CLKOUT, will drift over a 600 ppm range relative to the supplied reference clock. The LOL output will remain asserted until the recovered clock frequency is within the REFCLK frequency by the amount specified in Table 4.
Note: LOL is not asserted during PWRDN/CAL.
f0
f1
f2
Frequency
f3
ft
SONET Data Rate OC-48 OC-12 OC-3
F0 (Hz) 10 10 10
F1 (Hz) 600 30 30
F2 (Hz) 6000 300 300
F3 (kHz) 100 25 6.5
Ft (kHz) 1000 250 65
Figure 6. Jitter Tolerance Specification
Jitter Transfer The SI5020 is fully compliant with the relevant Bellcore/ ITU specifications related to SONET/SDH jitter transfer. Jitter transfer is defined as the ratio of output signal jitter to input signal jitter as a function of jitter frequency (see Figure 7). These measurements are made with an input test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in Figure 6. Jitter Generation The SI5020 exceeds all relevant specifications for jitter generation proposed for SONET/SDH equipment. The jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. The SI5020 typically generates less than 3.0 mUI rms of jitter when presented with jitter-free input data.
PLL Performance
The PLL implementation used in the SI5020 is fully compliant with the jitter specifications proposed for SONET/SDH equipment by Bellcore GR-253-CORE, Issue 2, December 1995 and ITU-T G.958. Jitter Tolerance The SI5020's tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 6. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device.
Note: There are no entries in the mask table for the data rate corresponding to OC-24 as that rate is not specified by either GR-253 or G.958.
Preliminary Rev. 0.8
11
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Jitter Transfer
When PWRDN/CAL is released (set to "low") the digital logic resets to a known initial condition, recalibrates the DSPLL, and will begin to lock to the data stream.
20 dB / Decade Slope Acceptable Range
0.1 dB
Device Grounding
The SI5020 uses the GND pad on the bottom of the 20pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figures 10 and 11 for the ground (GND) pad location.
Fc Frequency
Bias Generation Circuitry
The SI5020 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 k (1%) resistor connected between REXT and GND.
SONET Data Rate OC-48 OC-12 OC-3
Fc (kHz) 2000 500 130
Figure 7. Jitter Transfer Specification
Differential Input Circuitry
The SI5020 provides differential inputs for both the high speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 8. In applications where direct DC coupling is possible, the 0.1 F capacitors may be omitted. The DIN and REFCLK input amplifiers require an input signal with a minimum differential peak-to-peak voltage listed in Table 2 on page 6.
Power Down
The SI5020 provides a power down pin, PWRDN/CAL, that disables the output drivers (DOUT, CLKOUT). When the PWRDN/CAL pin is driven "high", the positive and negative terminals of CLKOUT and DOUT are each tied to VDD through 100 on-chip resistors. This feature is useful in reducing power consumption in applications that employ redundant serial channels.
Differential Driver
SI5020
VDD 0.1 F DIN+, REFCLK+ 2.5 k
Zo = 50
10 k 0.1 F Zo = 50 DIN-, REFCLK-
2.5 k
102
10 k
GND
Figure 8. Input Termination for DIN and REFCLK (AC Coupled)
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Preliminary Rev. 0.8
SI5020
Differential Output Circuitry
The SI5020 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with AC coupling is shown in Figure 9. In applications in which direct DC coupling is possible, the 0.1 F capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 6.
SI5020
VDD 100 DOUT+, CLKOUT+ 0.1 F 50 Zo = 50
VDD
DOUT-, CLKOUT-
0.1 F
Zo = 50
100 VDD
50
VDD
Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled)
Preliminary Rev. 0.8
13
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Pin Descriptions: SI5020
RATESEL1 RATESEL0 CLKOUT+ CLKOUT-
20 19 18
REXT VDD GND REFCLK+ REFCLK-
GND
17 16 15 PWRDN/CAL 14 VDD
1 2 3 4 5 6
LOL
GND Pad
13 DOUT+ 12 DOUT- 11 VDD
7
VDD
8
GND
9
DIN+
10
DIN-
Top View
Figure 10. SI5020 Pin Configuration
Table 9. SI5020 Pin Descriptions
Pin # 1 Pin Name REXT I/O Signal Level Description External Bias Resistor. This resistor is used by onboard circuitry to establish bias currents within the device. This pin must be connected to GND through a 10 k (1%) resistor. 4, 5 REFCLK+, REFCLK- I See Table 2 Differential Reference Clock. The reference clock sets the initial operating frequency used by the onboard PLL for clock and data recovery. Additionally, the reference clock is used to derive the clock output when no data is present. O LVTTL Loss of Lock. This output is driven high when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 8. 9, 10 DIN+, DIN- I See Table 2 Differential Data Input. Clock and data are recovered from the differential signal present on these pins. 12, 13 DOUT-, DOUT+ O CML Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN. It is phase aligned with CLKOUT and is updated on the rising edge of CLKOUT.
6
LOL
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Preliminary Rev. 0.8
SI5020
Table 9. SI5020 Pin Descriptions (Continued)
Pin # 15 Pin Name PWRDN/CAL I/O I Signal Level LVTTL Power Down. To shut down the high-speed outputs and reduce power consumption, hold this pin high. For normal operation, hold this pin low. Calibration. To initiate an internal self-calibration, force a highto-low transition on this pin. (See "PLL Self-Calibration" on page 10.)
Note: This input has a weak internal pulldown.
Description
16, 17
CLKOUT-, CLKOUT+
O
CML
Differential Clock Output. The output clock is recovered from the data signal present on DIN. In the absence of data, the output clock is derived from REFCLK.
19, 20
RATESEL1, RATESEL0
I
LVTTL
Data Rate Select. These pins configure the onboard PLL for clock and data recovery at one of four user selectable data rates. See Table 7 for configuration settings.
Note: These inputs have weak internal pulldowns.
2, 7, 11, 14 3, 8, 18, and GND Pad
VDD GND
2.5 V GND
Supply Voltage. Nominally 2.5 V. Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 20-pin micro leaded package (see Figure 11) must be connected directly to supply ground.
Preliminary Rev. 0.8
15
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Ordering Guide
Table 10. Ordering Guide Part Number SI5020-BM Package 20-pin MLP Temperature -40C to 85C
16
Preliminary Rev. 0.8
SI5020
Package Outline
Figure 11 illustrates the package details for the SI5020. Table 11 lists the values for the dimensions shown in the illustration.
TO P VIEW
A D D /2 10 0 .0 5 D1 A A1 D 1 /2 2X N 0 .2 5 C B 4X P 5 6 1 0 .5 0 D IA . 2 3 E1 E 4X Q E 1 /2 E /2 1 2 3 (N e-1 )X e E2 REF. A2 A3 N R D2 D 2 /2 8. C 4X P b 4 0 .1 0
M
2X 0 .2 5 C A
BO TTO M VIEW
CA B
E 2 /2 L 0 .2 0 2X C B B 0 .2 0 2X b 4 C C L C C L A1 11 C A 0 e S E A T IN G PLANE (N d -1 )X e REF.
C
NO TES: 1. 2. DIE THICKNESS ALLO W ABLE IS 0.305mm MA XIMUM(.012 INCHES MAXIMUM ) DIMENSIO NING & TO LERANCES CO NFO RM T O ASME Y14.5M. - 1994. N IS THE NUMB ER O F TERMINALS. Nd IS THE NUM BER O F TERMINALS IN X-DIR ECTIO N & Ne IS THE NUM BER O F TERMINALS IN Y-DIR ECTIO N. DIMENSIO N b A PPLIES TO PLATED TERMINA L AND IS MEASURED BETW EEN 0.20 AND 0.25mm FRO M TERMINA L TIP.
SEC TIO N "C -C "
SCALE: NONE
3.
e
e
4.
T E R M IN A L T IP
5.
FO R EVEN TER M IN AL/SID E
THE PIN #1 IDE NTIFIER MUST BE EXISTED O N THE TO P SURFACE O F THE PACKAG E BY U SING INDENTATIO N MARK O R O THER FEATURE O F PACKA G E BO DY.
FO R O D D TER M IN AL/SID E
6. 7. 8. 9. 10.
EXACT SHAPE AND SIZE O F THIS FEATURE IS O PTIO NAL. ALL DIMENSIO N S ARE IN MILLIMETERS. THE SHAPE SH O W N O N FO UR CO RNERS AR E NO T ACTUAL I/O . PACKAG E W AR PAG E MAX 0.05mm. APPLIED FO R E XPO SED PAD AND TERMINAL S. EXCLUDE EMB EDDING PART O F EXPO SED PAD FRO M MEA SURING .
11.
APPLIED O NLY FO R TERMINALS.
Figure 11. 20-pin Micro Leaded Package (MLP) Table 11. Package Diagram Dimensions Symbol A A1 A2 A3 b D D1 D2 e E Min -- 0.00 -- 0.23 Millimeters Nom 0.85 0.01 0.65 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 0.50 BSC 4.00 BSC Max 1.00 0.05 0.80 0.35 Symbol Min E1 E2 N Nd Ne L P Q R 1.95 Millimeters Nom 3.75 BSC 2.10 20 5 5 0.60 0.42 0.40 0.17 -- Max 2.25
1.95
2.25
0.50 0.24 0.30 0.13 --
0.75 0.60 0.65 0.23 12
Preliminary Rev. 0.8
17
S i5 02 0
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
18
Preliminary Rev. 0.8

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